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Digital media / CPU cache / DIMM / DDR SDRAM / Synchronous dynamic random-access memory / Memory controller / Dynamic random-access memory / Dell Dimension / Intel Xeon chipsets / Computer memory / Computer hardware / Computing


IBM “MXT” Memory Compression Technology Debuts in a ServerWorks Northbridge R. Brett Tremaine Senior Technical Staff Member IBM, TJ Watson Research Center Yorktown Heights, NY
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Document Date: 2013-07-27 23:38:03

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File Size: 244,79 KB

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IBM / Cisco / Cache / /

Currency

USD / /

Facility

CIOB Dual PCI Bridge / Dual PCI Bridge / port SRAM / /

IndustryTerm

real-time hardware compression / contemporary technologies / real-time 1KB physical memory block compression / volume server / Online Maintenance / /

OperatingSystem

L3 / /

Person

Kwok-Ken Mak / Dual Ported On-Chip / R. Brett Tremaine / Michael Wazlowski / /

Position

Manager Unit Hardware Data Compressor/Decompressor / MXT Technology CNB30HE Internal Architecture processor bus controller / memory controller / Hardware Memory Manager / Controller / /

ProvinceOrState

New York / California / /

RadioStation

168 2GB / 91 2GB / /

Technology

Memory Compression Technology / DDR SDRAM / Full-Duplex / SDRAM / 4 Processors / SRAM / /

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