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Central processing unit / Microprocessors / Threads / Parallel computing / CPU cache / Multithreading / Microarchitecture / Cache / Simultaneous multithreading / Computing / Computer hardware / Computer architecture


Analysis of Multithreaded Architectures for Parallel Computing Rafael H. Saavedra-Barrera David E. Culler Thorsten von Eicken Computer Science Division
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Document Date: 2003-06-11 14:31:52


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City

Jerusalem / Honolulu / Stockholm / /

Company

Section 7 / IBM / Russell / /

Country

West Germany / Israel / Sweden / /

Event

Reorganization / /

Facility

Parallel Computing Rafael H. Saavedra-Barrera David E. Culler Thorsten von Eicken Computer Science Division University of California Berkeley / University of California / /

IndustryTerm

acceptable solution / directory-based cache coherency protocol / conventional single context processor / context processor / conventional single-threaded processor / Concrete solutions / stochastic solution / particular solution / context on-chip / numerical solutions / /

MarketIndex

case 100 / /

Organization

University of California / National Science Foundation / National Aeronautics and Space Administration / Stanford / /

Person

Herve Touati / David Cross / Bob Boothe / Jose A. Ambros-Ingerson / /

Position

machine designer / /

Product

Nd / /

ProgrammingLanguage

K / /

ProvinceOrState

Florida / Hawaii / California / /

PublishedMedium

The International Journal / /

Technology

directory-based cache coherency protocol / one processor / an analytical model of multithreaded processor / Cache Memory / one context on-chip / simulation / context processor / /

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