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SerDes
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#	Item
51	A High Speed Quantum Communication Testbed Add to Reading List Source URL: w3.antd.nist.gov Language: English - Date: 2009-02-03 16:25:19 Quantum mechanics Applied mathematics Cryptography Quantum key distribution BB84 Qubit SerDes Quantum information Noisy-storage model Quantum cryptography Quantum information science Theoretical computer science
52	High-Speed Differential I/O Interfaces and DPA in Arria II Devices - Arria II Device Handbook, Volume 1, Chapter 8 Add to Reading List Source URL: www.altera.com Language: English - Date: 2012-07-20 05:40:13 Electronics Low-voltage differential signaling SerDes ETX Altera PCI Express Field-programmable gate array Phase-locked loop Computer hardware Electronic engineering Computer buses
53	AN 572: Implementing the Scalable SERDES Framer Interface (SFI-S) Protocol in Stratix IV GT Devices AN[removed] © January 2010 Add to Reading List Source URL: www.altera.com Language: English - Date: 2010-01-06 18:06:42 Networking hardware Technology SerDes Framer Interface Ethernet Digital electronics Altera Optical Internetworking Forum SerDes Field-programmable gate array Electronic engineering Electronics Fiber-optic communications
54	AN 573: Implementing the Interlaken Protocol in Stratix IV Transceivers © December 2009 AN[removed] Add to Reading List Source URL: www.altera.com Language: English - Date: 2009-12-28 17:31:45 Ethernet Field-programmable gate array Digital electronics Wireless sensor network Altera SerDes Universal asynchronous receiver/transmitter Interlaken Phase-locked loop Electronic engineering Electronics Technology
55	Transceiver Protocol Configurations in Cyclone V Devices Add to Reading List Source URL: www.altera.com Language: English - Date: 2013-10-17 23:34:01 PCI Express OSI protocols Nvidia SerDes Nvidia Ion XAUI Computer hardware Computer buses Standards organizations
56	Transceiver Architecture in Cyclone V Devices Add to Reading List Source URL: www.altera.com Language: English - Date: 2013-05-03 17:33:16 Networking hardware Integrated circuits PCI Express Transceiver Field-programmable gate array Altera SerDes PHY Phase-locked loop Electronic engineering Electronics Computer buses
57	1. Cyclone IV Transceivers Architecture October 2013 CYIV[removed]CYIV[removed]Cyclone® IV GX devices include up to eight full-duplex transceivers at serial data Add to Reading List Source URL: www.altera.com Language: English - Date: 2013-10-10 18:08:31 Computer buses Standards organizations Ethernet SerDes Field-programmable gate array XAUI 8b/10b encoding Altera PCI Express Computer hardware Electronic engineering Electronics
58	High Bandwidth, Low Power, and Low BER Altera’s 28-nm, Power-Efficient Transceivers Altera® transceivers have a proven track record of meeting system bandwidth, power, and bit-error rate (BER) requirements. This tech Add to Reading List Source URL: www.altera.com Language: English - Date: 2013-01-24 16:19:18 Technology Ethernet Altera XAUI Field-programmable gate array Jitter Interlaken SerDes Framer Interface QSFP Electronics Electronic engineering Networking hardware
59	Extending Transceiver Leadership at 28 nm WP[removed]White Paper Add to Reading List Source URL: www.altera.com Language: English - Date: 2012-10-31 18:06:56 Electromagnetism Altera Digital electronics Networking hardware Field-programmable gate array Jitter Backplane SerDes Phase-locked loop Electronic engineering Electronics Computer buses
60	 Parasti nosaka darba „pamatlaiku”, jeb „serdes laiku”(10:00-15:00), kurā nodarbinātajam noteikti jābūt darbā (parasti šajā laikā rīko sanāksmes, darba grupu tikšanās u.tml.), taču pārējo darb Add to Reading List Source URL: www.mk.gov.lv Language: Latvian - Date: 2015-04-05 01:49:39

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