Back to Results
First PageMeta Content
Computer hardware / 64-bit / CPU cache / Instruction set / Scalar processor / CDC Cyber / Comparison of CPU architectures / Computer architecture / Computing / Central processing unit


HC17.S4T1 Telairity-1 A Real Time H.264 High Definition Video Architecture.ppt
Add to Reading List

Document Date: 2013-07-27 23:46:07

Open Document

File Size: 375,85 KB

Share Result on Facebook

Currency

pence / /

IndustryTerm

real time / video applications / vector/scalar processors / /

NaturalFeature

Arbiter Parallel Input Channel Parallel Output Channel / /

Organization

Four Pipe Unit / Instruction Unit / Independent Scalar Unit / /

Person

Richard Dickson / /

Position

video compression P0 P3 P1 Video Controller DRAM Controller / loosely coupled MP / O Architecture Processor P2 I/O Arbiter / DRAM controller / video controller / MB SDRAM Controller / /

Technology

vector/scalar processors / SDRAM / HD Telairity-1 I/O Architecture Processor / video conferencing / SRAM / /

SocialTag