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Network On Chip / Routing / Wormhole switching / OSI protocols / Throughput / Router / Network switch / Forwarding plane / Load-balanced switch / Network architecture / Computing / Flow control


A Delay Model for Router Micro-architectures Li-Shiuan Peh William J. Dally
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Document Date: 2005-12-01 13:38:05


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File Size: 189,83 KB

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City

San Francisco / Palo Alto / /

Company

Distributed Systems / Cambridge University Press / MIT Press / Synopsys / /

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Facility

port Figure / /

IndustryTerm

basic virtualchannel router / abstract routers / i.e. router / wormhole vs. virtual-channel routers / wormhole router / virtual channel routers / virtual-channel routers / canonical wormhole router / speculative virtual-channel router / micron technology / virtual cut-through routers / basic virtual-channel router / virtualchannel router / mesh network / virtual-channel router / /

Organization

Cambridge University / MIT / Stanford University Stanford / /

Person

William J. Dally / Andrew A. Chien / Kevin Bolding / Pedro Lopez / C. Sequin / Jose Duato / Ivan Sutherland / David Harris / Morgan Kaufman / Bob Sproull / /

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Position

editor / Wormhole router Switch arbiter / global switch arbiter / arbiter / sw arbiter / model / designer / input controller / switch arbiter / matrix arbiter / controller / /

ProgrammingLanguage

Verilog / /

Technology

0.18 micron technology / virtual channel routers / 2-dimensional virtual-channel router / k-ary ncube Wormhole Routers / Constant-Area Routers / 9 2 1 Wormhole router / canonical wormhole router / speculative virtual-channel router / virtual-channel routers / virtual-channel router / basic virtual-channel router / wormhole router / virtual cut-through routers / basic virtualchannel router / 0 8.4 10.5 Virtual-channel router / Verilog / flow control / i.e. router / virtualchannel router / wormhole vs. virtual-channel routers / Simulation / /

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