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| First Page | Document Content | |
|---|---|---|
 Date: 2015-02-02 14:11:43Electronics Aldec Systems engineering Requirements traceability Traceability Requirement Change impact analysis Field-programmable gate array Application-specific integrated circuit Software requirements Electronic engineering Technology |
| Microsoft Word - Aldec_HES-7_FebdocxDocID: 1swBS - View Document |
| Product Line High-Performance Simulator for Mixed Language Designs IEEE VHDL, SystemVerilog, Verilog-AMS, SystemC/C/C++ Verification EcosystemDocID: 1kDAH - View Document |
| CyberWorkBench® High-Level Synthesis and Verification by: SystemC High-Level Synthesis and VerificationDocID: 1amXJ - View Document |
| RTAX_DatasheetPP1_Rev2012.02DocID: 1acQY - View Document |
| HES-DVM™ HW/SW Validation Platform Hybrid Verification Platform HES-DVMTM is a Hybrid Verification and Validation Platform for Hardware and Software developers of SoC and ASIC designs up to 144M ASIC gates. UtilizingDocID: 1aarU - View Document |