Back to Results
First PageMeta Content
Computer hardware / Rendering / CPU cache / Ray casting / Scene graph / Distributed ray tracing / Bounding interval hierarchy / 3D computer graphics / Computing / Ray tracing


RayCore: A ray-tracing hardware architecture for mobile devices JAE-HO NAH Sejong University and University of North Carolina at Chapel Hill and HYUCK-JOO KWON and DONG-SEOK KIM
Add to Reading List

Document Date: 2014-05-02 04:54:08

Open Document

File Size: 499,45 KB

Share Result on Facebook

Company

JINHONG PARK LG Electronics / GPU / TSMC / Table I. Hardware / Synopsys / NVIDIA / Samsung / Xilinx / Intel / Dynalith Systems / /

Currency

pence / /

Event

Reorganization / /

Facility

DINESH MANOCHA University of North Carolina / I pipeline / MIMD pipeline / Building Unit / Pipeline In / TACK-DON HAN Yonsei University / University of North Carolina / Chapel Hill / JAE-HO NAH Sejong University / T&I pipeline / DONG-SEOK KIM Sejong University / /

IndustryTerm

ray-tracing hardware / semiconductor technology / classic global illumination algorithm / laptop systems / unit energy / resource-limited mobile hardware / parallel kd-tree construction algorithm / mobile application processors / nm process technology / times greater energy efficiency / real-time mobile ray tracing / software simulations / real-time ray tracing algorithms / selective ascending algorithms / memory systems / 3D applications / reconfigurable processor / software-based ray tracing systems / real-time rendering / setup processing / fabrication technology / graphics hardware / parallelization algorithms / reconfigurable processors / pre-computation-based intersection algorithm / intersection test algorithm / dedicated ray-tracing hardware / software architectures / visual computing / multi-threading systems / /

NaturalFeature

Chapel Hill / /

OperatingSystem

Fermi / TRaX / /

Organization

FPGA / Ray Tracing Unit / University of North Carolina / Yonsei University / Sejong University / Tree-Building Unit for Dynamic Scenes In / ASIC / BuildLQJ Unit / /

Person

Marko Dabrovic / WOO-CHAN PARK / DONG-SEOK KIM / CHEOL-HO JEONG / JAE-HO NAH / Static Dynamic / Tack-Don Han / JOO KWON / Anat Grynberg / Greg Ward / Dinesh Manocha / /

Position

Manager / General / SRAM controller / memory controller / controller / /

Product

OpenGL ESbased applications / Wald / OpenGL ESbased / /

ProgrammingLanguage

K / /

ProvinceOrState

Manitoba / North Carolina / /

PublishedMedium

ACM Transactions on Graphics / the PCI Express / /

RadioStation

Core 2 / /

Technology

alpha / FPGA / visual computing / FPGA chip / mobile application processors / reconfigurable processor / real-time ray tracing algorithms / Graphics processors / desktop processors / semiconductor technology / API / present two parallelization algorithms / parallel kd-tree construction algorithm / selective ascending algorithms / Virtex-6 LX550 FPGA chips / random access / SRAM / mobile devices / ASIC / reconfigurable SIMT processor / illumination algorithm / proposed algorithm / 2.3 Kd-tree Construction Algorithms / 28 nm process technology / smartphones / intersection test algorithm / Apple A7 processor / 3D graphics / pre-computation-based intersection algorithm / simulation / fabrication technology / /

URL

http /

SocialTag