Parallel array - Document - PDFSEARCH.IO

First Page		Document Content
Date: 2006-09-22 00:58:27 Electronics Parallel computing Computer architecture Fabless semiconductor companies Mitrionics Field-programmable gate array High-performance reconfigurable computing Xilinx Multi-core processor Electronic engineering Computing Reconfigurable computing		Add to Reading List Source URL: sc06.supercomputing.org Download Document from Source Website File Size: 444,25 KB Share Document on Facebook

	High Performance ECC over NIST Primes on Commercial FPGAs ECC 2008, Utrecht, September 22-24, 2008 Tim Güneysu Horst Görtz Institute for IT-Security Ruhr University of Bochum, Germany DocID: 1lrAU - View Document
	3rd Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2013): Category 2 A High-Performance Oblivious RAM Controller on the Convey HC-2ex Heterogeneous Computing Platform Martin Maas, DocID: 1kJVR - View Document
	SDPS Journal http://hartenstein.de/SDPS/SDPSjournal.html Transactions of the SDPS: Integrated Design & Process Science DocID: 18fKC - View Document
	1 An XML Schema for Representing Reusable IP Cores for Reconfigurable Computing Nathaniel Rollins, Adam Arnesen, and Michael Wirthlin NSF Center for High-Performance Reconfigurable Computing (CHREC) DocID: 17XXr - View Document
	A MULTI-LAYERED XML SCHEMA AND DESIGN TOOL FOR REUSING AND INTEGRATING FPGA IP Adam Arnesen, Nathaniel Rollins, and Michael Wirthlin NSF Center for High-Performance Reconfigurable Computing (CHREC) Dept. of Electrical an DocID: 17RRQ - View Document