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OpenRISC / Hardware description languages / OpenCores / Verilator / Embedded systems / Open source / Open-source hardware / Linux / Joint Test Action Group / Electronic engineering / Electronics / Embedded microprocessors


Open Source Software Meets Open Source Hardware OpenCores and the OpenRISC 1000 Jeremy Bennett, CEO Embecosm Julius Baxter, OpenRISC Program Manager, OpenCores.org 17 October 2011
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Document Date: 2013-01-16 23:54:46

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Company

Creative Commons / Memory Controller UART Peripheral A OR1200 / Licensing Open Source Hardware / ORPSoC Clock / OpenCores / ORSoC AB / /

Facility

Linux port / /

IndustryTerm

to this hardware / tool chain / back end tools / software tools / bare metal / contract law / front end tools / software development / /

OperatingSystem

BSD / Linux / GNU / /

Organization

Harvard / Debug Unit / Stanford / /

Person

Damjan Lampret / Embecosm Julius Baxter / Wishbone Bus / /

Position

CEO / cycle-accurate model / Manager / OpenCores.org / GNU Lesser General Public License / Arbiter / OpenRISC Program Manager / /

ProgrammingLanguage

Verilog / J / C++ / /

Technology

Verilog / System-on-Chip / Linux / JTAG / simulation / RTOS / operating systems / /

URL

www.opencores.org / www.openrisc.net / /

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