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Journal of Cryptographic Engineering manuscript No. (will be inserted by the editor) A Preliminary FPGA Implementation and Analysis of Phatak’s Quotient-First Scaling Algorithm in the Reduced-Precision Residue Number S
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Document Date: 2014-12-18 10:27:44

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File Size: 267,56 KB

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Washington / DC / Berlin / London / /

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Network Theory Ltd. / Cryptographic Hardware / Embedded Systems / Cox / Xilinx / /

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United States / United Kingdom / /

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IDR / /

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Facility

A.T. Sherman Cyber Defense Lab University of Maryland / University of Maryland / /

IndustryTerm

digital signature algorithms / conventional hardware / straightforward division algorithm / sign-detection algorithm / synthesis tool / quotient-first scaling algorithm / partial reconstruction algorithm / equivalent sequential hardware / multiplication algorithm / exponentiation algorithm / software simulation / exponentiation algorithms / convergence division algorithms / hardware / Residue number systems / /

Organization

National Science Foundation / ASIC / University of Maryland / Baltimore County / IEEE Computer Society / /

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David DeLatte / Christopher D. Nguyen / Chintan Patel / Ryan Robucci / Alan T. Sherman / Steven D. Houston / T. Sherman Cyber / /

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editor / controller / /

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Python / DC / /

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Maryland / Baltimore County / /

PublishedMedium

Mathematics of Computation / /

Technology

FPGA / RP-RNS scaling algorithm / mod D. The QFS algorithm / sign-detection algorithm / 1 Algorithm / exponentiation algorithms / Levenberg-Marquardt algorithm / RP-RNS algorithms / exponentiation algorithm / RSA algorithm / encryption / cryptography / partial reconstruction algorithm / D. The algorithm / ASIC / QFS algorithm / Scaling algorithm / 12.16508 The QFS algorithm / 2 Algorithms / RP-RNS partial reconstruction algorithm / multiplication algorithm / ME algorithm / digital signature algorithms / RP-RNS QFS algorithm / simulation / RNS algorithms / Q. The QFS algorithm / /

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