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Computing / Computer memory / CPU cache / Cache / Translation lookaside buffer / Microarchitecture / Runway bus / PA-8000 / R8000 / Computer hardware / Central processing unit / Computer architecture


Document Date: 2004-09-18 17:27:43

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City

Fort Collins / /

Company

Cupertino Systems Laboratory / Systems Performance Laboratory / Engineering Systems Laboratory / Hewlett-Packard / Computer Technology Laboratory / California Languages Laboratory / /

Facility

Cupertino Systems Laboratory / Computer Technology Laboratory / Store Merger / Engineering Systems Laboratory / California Languages Laboratory / Systems Performance Laboratory / /

IndustryTerm

minimal hardware / interface chips / transaction processing benchmarks / software prefetching mechanisms / double snoop† algorithm / natural solutions / typical analytic and scientific applications / gate-shrink algorithm / Large analytic applications / corporate computing platforms / manufacturing cost / ratio algorithm / multiprocessor systems / manufacturing constraints / coherent transaction management / tighter metal pitch / processor chip / real-world applications / metal / off-chip / reasonable tool / transaction processing applications / target technology / process technology / store-intensive applications / superscalar processor / metal interconnect technology / translation algorithm / instruction prefetch algorithm / hardware prefetching algorithms / /

MusicAlbum

I/O / /

Organization

Address I-cache Tag SRAMs Floating-Point Unit / Integrated Circuits Business Division / /

Person

TLB READ / Francis X. Schumacher / Gordon P. Kurpanek / John R. Keller / Cyrus C. Hay / Kenneth K. Chan / Jason Zheng / /

Position

Driver / Integrated High-Performance MP / head / CPU Data Cache SRAMs Runway Bus Bus Converter Memory Controller / Dual-Rail MUX Address Driver / memory controller / /

Product

7100LC / RAM / CMOS26 / /

ProvinceOrState

California / Colorado / /

Technology

double snoop† algorithm / gate-shrink algorithm / detailed algorithm / RAM / ratio algorithm / designed PA-RISC1 / 2 processors / 7200 processor / 7200 CPU Data Cache SRAMs Runway Bus Bus Converter Memory Controller Processor / JTAG / existing CMOS26 technology / translation algorithm / processor chip / SRAM / instruction prefetch algorithm / process technology / Integrated Circuits / interface chips / little-endian / 7200 CPU chip / 7200 CPU Processor / three-level metal interconnect technology / CMOS PA-RISC Processor / 7200 processor chip / one processor / flow control / target technology / 7200 chip / hardware prefetching algorithms / simulation / superscalar processor / 7100 processors / 7200 VLSI chip / designed using the existing CMOS26 technology / /

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