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Central processing unit / Microprocessors / Microarchitecture / Datapath / Register file / Parallel computing / Cell / Multi-core processor / Superscalar / Computer architecture / Computer engineering / Computer hardware


Document Date: 2002-07-23 17:31:53

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File Size: 66,71 KB

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Company

Synopsys / Control Data / PIM-Based Systems / HP / Virage Logic / TSMC / /

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Facility

The WideWord Processor pipeline / M. Hall / /

IndustryTerm

video applications / host processor / conventional systems / node processor / pixel processing / host software / node processing logic / sparse-matrix applications / communications bandwidth / computing / permutation network / on-chip memory bank / wide on-chip / memory device / software architecture / technology trend / internal processors / scalar processor / prototype chip / target applications / /

Organization

Cadence Silicon Ensemble / Jeff Sondeen USC Information Sciences Institute / University of Southern California / DIVA PIM / /

Person

Morgan Kaufman / Jeff Sondeen / /

Position

controller / Arbiter / programmer / /

ProvinceOrState

Southern California / /

PublishedMedium

IEEE Spectrum / /

Region

Southern California / /

Technology

wide on-chip / Memory Bus Host Processor / host processor / SDRAM protocol / PIM processor / DIVA prototype chip / PIM technology / DIVA PIM chips / PIM chip / gigabit / SRAM / scalar processor / 256-bit WideWord Processor / Microarchitecture overview Each DIVA PIM chip / 0.18µm technology / VHDL / node processor / DIVA PIM prototype chip The chip / /

URL

http /

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