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Central processing unit / Compiler optimizations / Classes of computers / Instruction set architectures / Software pipelining / Instruction pipeline / Reduced instruction set computing / MIPS architecture / Microarchitecture / Computer architecture / Computing / Computer engineering


Improving Low Power Processor Efficiency with Static Pipelining Ian Finlayson† , Gang-Ryung Uh‡ , David Whalley† and Gary Tyson† † ‡
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Document Date: 2011-01-31 11:18:06

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File Size: 147,75 KB

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Washington / DC / Braga / Austin / /

Company

RTL / Cambridge Univ Press / /

Country

United States / Portugal / /

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Facility

VPO MIPS port / Computer Science Florida State University / MIPS port / C library / /

IndustryTerm

software pipelining / lower energy cost / energy consumption / reduced energy consumption / energy-efficiency / less energy consumption / Energy-efficient register access / pipe-lined processor / energy-efficient manner / energy consumption values / processor energy consumption / mobile devices / simpler hardware / conventional processor / energy reduction / energy savings / overlapped using software pipelining / /

OperatingSystem

GNU / /

Organization

National Science Foundation / Boise State University / Florida State University / Cambridge Philosophical Society / IEEE Computer Society / /

Person

M. Kudlur / Embedded Benchmark / Gang-Ryung Uh / S. Mahlke / Gary Tyson / David Whalley / /

Position

Representative / WB / MEM WB / /

ProgrammingLanguage

Verilog / DC / C / /

Technology

Improving Low Power Processor / Verilog / statically pipe-lined processor / conventional processor / micro-programmed processor / caching / DSP / Integrated circuits / Digital Signal Processors / two-stage processor / mobile devices / /

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