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Computing / Central processing unit / Computer architecture / CPU cache / Cache / Parallel computing / MSI protocol / False sharing / Cache coherency / Computer memory / Computer hardware


Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically ∗ Abdullah Muzahid† , Shanxiang Qi, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Abstra
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Document Date: 2012-11-04 16:19:00

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B CR CW D CO / MySQL / NC S CO / NC D CO / Intel / CR S CO CO / CW D CO CO / /

Currency

pence / /

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Facility

University of Texas / Josep Torrellas University of Illinois / Architecture Core pipeline ROB / /

IndustryTerm

enough hardware / race-detection tool / cache coherence protocol / conventional race-detection tools / /

OperatingSystem

Microsoft Windows / /

Organization

University of Texas at San Antonio / University of Illinois / National Science Foundation / PA AS / PA ’s PP / SESC / Illinois-Intel Parallelism Center / /

Person

Harris Pthread / Ai / Abdullah Muzahid / Tail Hash / /

Position

Prime Minister / controller / and multi-word cache lines / writer / WB / Private / producer / controller / programmer / Head / /

ProgrammingLanguage

Java / RC / /

ProvinceOrState

Texas / Pennsylvania / South Carolina / Illinois / /

Technology

cryptography / Java / Delay Set algorithm / two processors / Sequential Consistency / cache coherence protocol / /

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http /

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