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Computer architecture / CPU cache / MESI protocol / Cache / Central processing unit / MSI protocol / Write-once / Computing / Cache coherency / Computer hardware


Memory Barriers: a Hardware View for Software Hackers Paul E. McKenney Linux Technology Center IBM Beaverton [removed] April 5, 2009
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Document Date: 2009-04-06 00:30:49

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File Size: 288,15 KB

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Company

IBM / CPU / State Load Load Writeback RMW Store Atomic Inc / /

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Facility

Store Buffer / Store Buffer Cache / Store Sequences Result / Store Buffer Store Buffer Cache / Unnecessary Stalls / Store Buffers / Store Forwarding CPU / /

IndustryTerm

hash chain / cache-coherence protocol / mutual-exclusion algorithm / software types / software designers / cachecoherence protocol / memory systems / cache-coherency protocols / /

OperatingSystem

Sequent / Linux / /

Person

Paul E. McKenney / /

Position

smp_mp / /

Technology

2.4 MESI Protocol / Linux Technology / 2.2 MESI Protocol / cachecoherence protocol / cache-coherency protocols / mutual-exclusion algorithm / shared memory / Cache-Coherence Protocols Cache-coherency protocols / MESI cache-coherence protocol / /

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