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Computer hardware / Computer memory / CPU cache / MESI protocol / MSI protocol / Cache / Transactional memory / Parallel computing / Cache coherency / Computing / Concurrent computing


OmniOrder: Directory-Based Conflict Serialization of Transactions ∗ Xuehai Qian † University of California, Berkeley Benjamin Sahelices
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Document Date: 2014-04-19 12:44:14


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File Size: 358,57 KB

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Checkpoint / IBM / Oracle / Window CO / Azul / P’s / AMD / Intel / /

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Facility

Spain University of Illinois / University of Illinois / University of California / /

Holiday

Ramadan / /

IndustryTerm

software handler / cache-coherence protocol / hardware-software design / cycle-detection algorithm / basic cache coherence protocol / earlier processors / sucessor processor / directory protocol / coherence protocol / log software structure / snoopy-based cache coherence protocol / sharer processors / energy / hardware-software combination / concurrent algorithms / transaction-executing processors / ordinary protocol / successor chain / bank / consumer processor / log software / trivially-simple hardware / squashed processor / dependence chain / speculative state management / predecessor processor / cache coherence protocol / /

Organization

University of Illinois / Urbana-Champaign / National Science Foundation / University of California / Berkeley / University of Illinois / SESC / Illinois-Intel Parallelism Center / /

Person

Benjamin Sahelices Josep Torrellas / /

Position

cache controller / producer / Governor / last writer / writer / programmer / /

Product

L0 / /

ProgrammingLanguage

RC / /

ProvinceOrState

Illinois / South Carolina / California / /

Technology

L2 cache Manycore chip / squashed processors / OmniOrder algorithms / producer processor / MSI protocol / sucessor processor / squashed processor / predecessor processor / four processors / cache-coherence protocol / snoopy-based cache coherence protocol / broadcast-based protocol / two processors / four transaction-executing processors / cycle-detection algorithm / 64-processor chip / second processor / same OmniOrder protocol / cache coherence protocol / destination processors / update-based protocol / three transaction-executing processors / ordinary protocol / one processor / basic cache coherence protocol / consumer processor / committing processor / sharer processors / coherence protocol / two earlier processors / supplier processor / SMT processors / Sequential Consistency / MESI protocol / directory protocol / ordinary MSI directory protocol / local processor / /

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http /

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