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Instruction set architectures / X86 architecture / Central processing unit / Binary translation / Virtual machines / Loongson / X86 / MIPS architecture / QEMU / Computer architecture / Computing / System software


Document Date: 2009-09-28 03:49:02

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City

New York / Washington / DC / Support / Cambridge / Beijing / /

Company

IBM / Itanium-Based Systems / Transmeta Code Morphing Software / HP / RTL / Intel / /

Country

United States / China / /

Currency

USD / /

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Facility

Institute of Computing Technology / Key Laboratory of Computer System / Architecture Institute of Computing Technology / Graduate University of Chinese Academy / University of Wisconsin / /

IndustryTerm

on-chip network / complicated software translation methods / software design / software improvements / x86 floating point applications / software-based methods / software-based optimization methods / instruction-level distributed processing / associative search / hardware-software co-designed method / software binary translation performance / pure software-based binary translation system / pure software-based optimization methods / software direct block chaining technique / binary translation software / software direct block chaining method / multi-core processor / software binary translators / software-based binary translation system / hardware-software co-designed binary translation systems / corner case processing etc / software part / proposed hardware-software co-designed methods / point applications / software-based jump target prediction / pure software-based binary translation / software binary translation systems / software binary translation method / software architecture / processor hardware / hardware-software / /

MarketIndex

TOP value / CPU / TOP / /

Organization

Graduate University / Key Laboratory of Computer System / Computer System and Architecture Institute of Computing Technology / Chinese Academy of Sciences / Institute of Computing Technology / National Natural Science Foundation of China / Partial X86 Decode Unit / US Federal Reserve / B. Partial X86 Decode Unit / IEEE Computer Society / University of Wisconsin / /

Person

Evelyn Duesterwald / /

Position

software-based translator / Source Microbench Microbench Microbench EEMBC EEMBC Microbench SPEC CPU2006 SPEC CPU2006 SPEC CPU2006 SPEC CPU2006 SPEC CPU2006 Exec. / DDR2/DDR3 controller / and one HyperTransport controller / translator / Tdbt Tnative Exec. / software-based binary translator / BENCHMARKS Name Floating point IDCT Floating point FFT General Control Fixed point IDCT Fixed point FFT OS booting / binary translator / software binary translator / profile-directed binary translator / improved binary translator / General control program / pure software-based translator / /

ProgrammingLanguage

FP / Fortran / DC / C++ / /

ProvinceOrState

Wisconsin / /

PublishedMedium

Microprocessor Report / /

Technology

FPGA / virtual machine / Godson processor / superscalar RISC processors / RAM / Godson processors / AV / floating point unit / Godson-3 chip / Godson-3 processors / Crusoe / 100 32-item 64-item 128-item 80 A. Experiment Platform Godson-3 processors / operating system / RISC processors / ST 65nm CMOS technology / pdf / Godson-3 chips / MIPS processors / simulation / Godson-2 Processor / /

URL

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