First Page | Document Content | |
---|---|---|
![]() Date: 2013-03-18 09:59:28Electronic design automation Theoretical computer science Applied mathematics Temporal logic Logic in computer science Linear temporal logic Uclid Formal verification Logic synthesis Electronic engineering Problem solving Reasoning | Add to Reading List |
![]() | Continued Relevance of Bit-Level Verification Research R. Brayton, N. Een, A. Mishchenko Berkeley Verification and Synthesis Research Center EECS Dept., University of California, Berkeley IntroductionDocID: 1qs3F - View Document |
![]() | PDF DocumentDocID: 1m46n - View Document |
![]() | ATLAS: Automatic Term-Level Abstraction of RTL Designs Bryan A. Brady UC BerkeleyDocID: 1lQim - View Document |
![]() | The UCLID Decision Procedure? Shuvendu K. Lahiri and Sanjit A. Seshia Carnegie Mellon University, Pittsburgh, PA , Abstract. UCLID is a tool for term-level modeling and verifDocID: 1lvpU - View Document |
![]() | Appeared at DAC’03 A Hybrid SAT-Based Decision Procedure for Separation ∗ Logic with Uninterpreted Functions Sanjit A. SeshiaDocID: 1luPV - View Document |