Linearizability

Results: 416



#Item
101Model Checking of Linearizability of Concurrent List Implementations? ˇ Pavol Cern´ y1 , Arjun Radhakrishna1 , Damien Zufferey1 , Swarat Chaudhuri2 , and Rajeev Alur3

Model Checking of Linearizability of Concurrent List Implementations? ˇ Pavol Cern´ y1 , Arjun Radhakrishna1 , Damien Zufferey1 , Swarat Chaudhuri2 , and Rajeev Alur3

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Source URL: www.cis.upenn.edu

Language: English - Date: 2010-04-19 09:32:20
    102WTTM 2012, The Fourth Workshop on the Theory of Transactional Memory Vincent Gramoli University of Sydney Australia

    WTTM 2012, The Fourth Workshop on the Theory of Transactional Memory Vincent Gramoli University of Sydney Australia

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    Source URL: www.gsd.inesc-id.pt

    Language: English - Date: 2014-09-25 06:02:42
    103Self-Tuning Intel Transactional Synchronization Extensions Nuno Diegues and Paolo Romano, INESC-ID and Instituto Superior Técnico, University of Lisbon https://www.usenix.org/conference/icac14/technical-sessions/present

    Self-Tuning Intel Transactional Synchronization Extensions Nuno Diegues and Paolo Romano, INESC-ID and Instituto Superior Técnico, University of Lisbon https://www.usenix.org/conference/icac14/technical-sessions/present

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    Source URL: www.usenix.org

    Language: English
    104AI: A Lightweight System for Tolerating Concurrency Bugs Mingxing Zhang1 Yongwei Wu1 Shan Lu2,∗ Shanxiang Qi3,† Jinglei Ren1 Weimin Zheng1 1  Tsinghua National Laboratory for Information Science and Technology, Tsing

    AI: A Lightweight System for Tolerating Concurrency Bugs Mingxing Zhang1 Yongwei Wu1 Shan Lu2,∗ Shanxiang Qi3,† Jinglei Ren1 Weimin Zheng1 1 Tsinghua National Laboratory for Information Science and Technology, Tsing

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    Source URL: people.cs.uchicago.edu

    Language: English - Date: 2014-08-19 10:13:59
    105Performance Implications of Fence-Based Memory Models Hans-J. Boehm HP Labs  Simplified mainstream (Java, C++)

    Performance Implications of Fence-Based Memory Models Hans-J. Boehm HP Labs Simplified mainstream (Java, C++)

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    Source URL: hboehm.info

    Language: English - Date: 2014-02-06 19:37:32
    106Linearizability: A Correctness Condition for Concurrent Objects MAURICE P. HERLIHY and JEANNETTE Carnegie Mellon University  M. WING

    Linearizability: A Correctness Condition for Concurrent Objects MAURICE P. HERLIHY and JEANNETTE Carnegie Mellon University M. WING

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    Source URL: cs.brown.edu

    Language: English - Date: 2002-12-21 01:16:06
    107Opportunities and pitfalls of multi-core scaling using Hardware Transaction Memory∗ Zhaoguo Wang†, Hao Qian‡, Haibo Chen‡, Jinyang Li§ † School of Computer Science, Fudan University ‡ Institute of Parallel a

    Opportunities and pitfalls of multi-core scaling using Hardware Transaction Memory∗ Zhaoguo Wang†, Hao Qian‡, Haibo Chen‡, Jinyang Li§ † School of Computer Science, Fudan University ‡ Institute of Parallel a

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    Source URL: news.cs.nyu.edu

    Language: English - Date: 2013-07-16 15:24:14
    108Efficient Concurrency-Bug Detection Across Inputs Dongdong Deng Wei Zhang  Shan Lu

    Efficient Concurrency-Bug Detection Across Inputs Dongdong Deng Wei Zhang Shan Lu

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    Source URL: people.cs.uchicago.edu

    Language: English - Date: 2013-08-04 18:25:14
    109Deriving Linearizable Fine-Grained Concurrent Objects Martin Vechev Eran Yahav  IBM Research

    Deriving Linearizable Fine-Grained Concurrent Objects Martin Vechev Eran Yahav IBM Research

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    Source URL: www.cs.technion.ac.il

    Language: English
    110Using Restricted Transactional Memory to Build a Scalable In-Memory Database Zhaoguo Wang†, Hao Qian‡, Jinyang Li§, Haibo Chen‡ † School of Computer Science, Fudan University ‡ Institute of Parallel and Distri

    Using Restricted Transactional Memory to Build a Scalable In-Memory Database Zhaoguo Wang†, Hao Qian‡, Jinyang Li§, Haibo Chen‡ † School of Computer Science, Fudan University ‡ Institute of Parallel and Distri

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    Source URL: news.cs.nyu.edu

    Language: English - Date: 2014-07-24 14:38:57