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Parallel computing / Instruction set architectures / Opteron / Cray XT3 / Itanium / Cray / Instructions per second / Cell / FLOPS / Computing / Computer architecture / Supercomputers


Document Date: 2006-05-10 04:35:36

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City

Washington DC / /

Company

Dell / Oak Ridge National Laboratory / IBM / Fujitsu / NEC / HP / AMD / National Academies Press / Intel / Microsoft / Hitachi / /

Country

Germany / United States / Netherlands / USA / /

Currency

AMD / /

Event

Natural Disaster / /

Facility

Future Jack Dongarra University of Tennessee / Nuclear Reactor / Barcelona Supercomputer Center / Earth Simulator Center / /

IndustryTerm

concurrent software / logical processors / software base / computing / /

Organization

Barcelona Supercomputer Center Spain / National Research Council / DOE Oak Ridge Nat Lab / Nat Lab / National Aeronautics and Space Administration / University of Tennessee / Earth Simulator Center Japan / /

Person

Most / Lawrence Livermore Nat Lab / Craig Mundie / Pat Gelsinger / Thomas Watson / /

Position

programming model / /

Product

Intel 2005 2004 2003 / /

ProgrammingLanguage

L / J / FP / DC / /

ProvinceOrState

Tennessee / /

Technology

2007 2008 Hardware Threads Per Chip Cores Per Processor Chip / Alpha / 256 logical processors / 2009 2010 15 Commodity Processor / interconnect 5 Processor / Commodity processor / Gigabit Ethernet / /

URL

www.top500.org / /

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