<--- Back to Details
First PageDocument Content
Computer programming / Subtext / Reactive programming / Coherence / Programming language / Declarative programming / Assignment / Functional programming / Imperative programming / Software engineering / Computing / Programming paradigms
Date: 2013-09-04 17:58:50
Computer programming
Subtext
Reactive programming
Coherence
Programming language
Declarative programming
Assignment
Functional programming
Imperative programming
Software engineering
Computing
Programming paradigms

Coherent Reaction Jonathan Edwards MIT Computer Science and Artificial Intelligence Lab Abstract

Add to Reading List

Source URL: www.subtext-lang.org

Download Document from Source Website

File Size: 153,44 KB

Share Document on Facebook

Similar Documents

Partial-Coherence Abstractions for Relaxed Memory Models Michael Kuperstein Martin Vechev  Eran Yahav ∗

Partial-Coherence Abstractions for Relaxed Memory Models Michael Kuperstein Martin Vechev Eran Yahav ∗

DocID: 1xVDm - View Document

Learning gem5 – Part III Modeling Cache Coherence with Ruby and SLICC Jason Lowe-Power http://learning.gem5.org/ https://faculty.engineering.ucdavis.edu/lowepower/

Learning gem5 – Part III Modeling Cache Coherence with Ruby and SLICC Jason Lowe-Power http://learning.gem5.org/ https://faculty.engineering.ucdavis.edu/lowepower/

DocID: 1xUst - View Document

Checking Cache-Coherence Protocols with TLA+ Rajeev Joshi HP Labs, Systems Research Center, Palo Alto, CA. Leslie Lamport Microsoft Research, Mountain View, CA.

Checking Cache-Coherence Protocols with TLA+ Rajeev Joshi HP Labs, Systems Research Center, Palo Alto, CA. Leslie Lamport Microsoft Research, Mountain View, CA.

DocID: 1xUq9 - View Document

CACHE COHERENCE DIRECTORIES FOR SCALABLE MULTIPROCESSORS Richard Simoni Technical Report: CSL-TROctober 1992 Computer Systems Laboratory

CACHE COHERENCE DIRECTORIES FOR SCALABLE MULTIPROCESSORS Richard Simoni Technical Report: CSL-TROctober 1992 Computer Systems Laboratory

DocID: 1vmKd - View Document

A Memory Coherence Technique for Online Transient Error Recovery of FPGA Configurations Wei-Je Huang and Edward J. McCluskey CENTER FOR RELIABLE COMPUTING Computer Systems Laboratory, Department of Electrical Engineering

A Memory Coherence Technique for Online Transient Error Recovery of FPGA Configurations Wei-Je Huang and Edward J. McCluskey CENTER FOR RELIABLE COMPUTING Computer Systems Laboratory, Department of Electrical Engineering

DocID: 1vgLJ - View Document