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Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping Marco Ceriani, Simone Secchi, Antonino Tumeo, Oreste Villa and Gianluca Palermo Motivation Prototype features
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Document Date: 2013-12-16 15:05:06

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File Size: 2,17 MB

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Company

Oreste Villa Pacific Northwest National Laboratory / /

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IndustryTerm

software multi-threading / limited additional custom hardware / irregular applications / soft-core processors / scientific applications / knowledge discovery applications / regular and irregular applications / /

Organization

Politecnico di Milano / /

Person

Marco Ceriani / Simone Secchi / /

Position

hardware scheduler / global memory access scheduler / /

Technology

FPGA / RAM / /

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