¡fixltx2e¿ [v2.0a fixes to LaTeX (obsolete)] ¡!fixltx2e¿ [v1.0d LaTeX release emulation and tests] 1 The latexrelease package∗

Source URL: ctan.uniminuto.edu

SENDMAIL(8zm) SENDMAIL(8zm) NAME sendmail − zmailer sendmail emulation and mail submission interface

Source URL: www.zmailer.org

Restrictions of emulation the Aeroflex/UTMC UT80C196KD microcontrollers by the Phyton PICE-196 emulator with the P196-KD pod Function of UT80C196KD Implementation in

Source URL: www.phyton.com

KMU-innovativ: IKT SOFTWARESYSTEME; WISSENSTECHNOLOGIEN MIESYS Test- und Beschreibungsplattform zur Modellierung, Integration und Emulation von verteilten Systemen

Source URL: www.pt-it.pt-dlr.de

¡fixltx2e¿ [v2.0a fixes to LaTeX (obsolete)] ¡!fixltx2e¿ [v1.0d LaTeX release emulation and tests] 1 The latexrelease package∗

Source URL: repositorios.cpai.unb.br

Technical Committee AAL1 Circuit Emulation Over Packet Switched Networks Version 1.0

Source URL: www.broadband-forum.org

PICE–52 Getting Started Phyton, Inc. PICE–52 Getting Started

Source URL: www.phyton.com

• Commodore 64
• Embedded systems
• Retrocomputing
• Debugging
• In-circuit emulator
• MOS Technology SID
• Hardware emulation
• Universal Serial Bus
• SSF
• Computing
• Computer hardware
• Software

Cloudy Emulation – Efficient and Scalable Emulation-based Services I. Valizada, K. Rechert, K. Meier, D. Wehrle, D. v. Suchodoletz and L. Sabel, Albert-Ludwigs University FreiburgFreiburg i. B., Germany {isganda

Source URL: purl.pt

• Retrocomputing
• Virtual machines
• Emulator
• Virtualization
• VICE
• SSF
• UVC-based preservation
• Software
• System software
• Computing

NIST Net – A Linux-based Network Emulation Tool Mark Carson, Darrin Santay National Institute of Standards and Technology (NIST) , Abstract

Source URL: snad.ncsl.nist.gov

• Internet standards
• Computer architecture
• Packet Processing
• Transmission Control Protocol
• Latency
• Differentiated services
• Emulator
• Packet loss
• Hash table
• Computing
• Network architecture
• Network emulation

HES-DVM™ HW/SW Validation Platform Hybrid Verification Platform HES-DVMTM is a Hybrid Verification and Validation Platform for Hardware and Software developers of SoC and ASIC designs up to 144M ASIC gates. Utilizing

Source URL: www.aldec.com

• Hardware verification languages
• Aldec
• Logic design
• Hardware emulation
• Hardware description languages
• Field-programmable gate array
• Joint Test Action Group
• Mentor Graphics
• Application-specific integrated circuit
• Electronic engineering
• Electronic design automation
• Digital electronics