First Page | Document Content | |
---|---|---|
![]() Date: 2014-07-31 22:34:01Computer memory System on a chip Embedded microprocessors Instruction set architectures Integrated circuits Application-specific integrated circuit ARC Random-access memory CPU cache Cell | Add to Reading List |
![]() | arXiv:1404.3465v1 [cs.CR] 14 AprNetwork-on-Chip Firewall: Countering Defective and Malicious System-on-Chip Hardware Michael LeMay∗, Carl A. Gunter University of Illinois at Urbana-ChampaignDocID: 1v4ku - View Document |
![]() | myCSoC: Design Explorations With Your Configurable System on a ChipDocID: 1uSVe - View Document |
![]() | myCSoC: Design Explorations With Your Configurable System on a ChipDocID: 1uO2g - View Document |
![]() | Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip By Andreas Olofsson Adapteva Inc, Lexington, MA, USADocID: 1uuhM - View Document |
![]() | myCSoC: Design Explorations With Your Configurable System on a ChipDocID: 1udjC - View Document |