Chapter 2 The Power Processing Element (PPE)

First Page		Document Content
Date: 2014-03-08 01:47:32 Central processing unit Computer memory Instruction set architectures Cell Power Architecture CPU cache AltiVec Processor register Direct memory access Computer architecture Computing Computer hardware		Chapter 2 The Power Processing Element (PPE) Add to Reading List Source URL: www.springer.com Download Document from Source Website File Size: 506,63 KB Share Document on Facebook

	Optimization of Vertical and Horizontal Beamforming Kernels on the PowerPC G4 Processor with AltiVec Technology Young H. Cho, David Brunke, and Greg E. Allen Applied Research Laboratories: The University of Texas at Aust DocID: 1syza - View Document
	Symbolic Crosschecking of Floating-Point and SIMD Code Peter Collingbourne Cristian Cadar Paul H. J. Kelly DocID: 1pUTw - View Document
	SPU C/C++ Language Extensions Version 2.1 CBEA JSRE Series Cell Broadband Engine Architecture DocID: 1poLa - View Document
	Vertical and Horizontal Beamforming Kernels with AltiVec Technology Young H. Cho, David Brunke, Greg E. Allen, and Brian L. Evans* The University of Texas at Austin Austin, TXU.S.A DocID: 1pbcL - View Document
	3000 SERIES StarGate 3120 & 3120D PowerPC VXS Payload The StarGate 3120 & 3120D are the first FastCluster 3000 SERIES PowerPC AltiVec VXS payloads incorporating the latest improvements DocID: 1nW13 - View Document