A case study of FPGA mappers optimality

First Page		Document Content
Date: 2007-02-12 14:27:19 Electronic design Digital electronics Integrated circuits Field-programmable gate array Logic synthesis Xilinx Logic optimization Application-specific integrated circuit Algorithm Electronic engineering Electronics Electronic design automation		A case study of FPGA mappers optimality Add to Reading List Source URL: cadlab.cs.ucla.edu Download Document from Source Website File Size: 377,47 KB Share Document on Facebook

	On Solving Boolean Multilevel Optimization Problems∗ Josep Argelich INESC-ID Lisbon DocID: 1rsZm - View Document
	Verified Peephole Optimizations for CompCert Eric Mullen Daryl Zuniga University of Washington, USA DocID: 1rsFQ - View Document
	I N F S Y S R E S E A R C H R DocID: 1riTl - View Document
	Learning to Search Better than Your Teacher Kai-Wei Chang KCHANG 10@ ILLINOIS . EDU DocID: 1rfgn - View Document
	A DESCRIPTIVE TITLE, NOT TOO GENERAL, NOT TOO LONG Markus P¨uschel Department of Computer Science ETH Z¨urich Z¨urich, Switzerland The hard page limit is 6 pages in this style. Do not reduce font size or use other tri DocID: 1r8dX - View Document