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![]() Date: 1997-12-01 22:58:09Electrical engineering Clock signal Electrical circuits Oscillators SerDes Electronic design Phase-locked loop Signal integrity Clock skew Electronic engineering Electronics Digital electronics | Add to Reading List |
![]() | Case Study of Half Power, Multi Protocol SERDES in 28nm FDSOI Unparalleled Power Performance 1DocID: 1tfp9 - View Document |
![]() | Client: MoSys Contact: Kristine Perham & Michael Miller Project: Chip Estimates Article From: Lee Stein Date: March 5, 2010DocID: 1qqY5 - View Document |
![]() | Proposed VLBI Standard Hardware Interface Specification – VSI-H 11 May 2000 Table of Contents.DocID: 1ouQa - View Document |
![]() | 25-MarLev Uvarov MPC – SP Synchronization Procedure Petersburg Nuclear Physics Institute / University of FloridaDocID: 1gD1o - View Document |
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