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Central processing unit / Models of computation / Dataflow architecture / CPU cache / Dataflow / Parallel computing / Cell / Instruction set / Trie / Computer architecture / Computing / Computer engineering


Department of Electrical and Computer Systems Engineering Technical Report MECSE
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Document Date: 2007-11-01 21:55:37

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File Size: 759,49 KB

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City

Manchester / Amsterdam / /

Company

Prentice-Hall / Xilinx Incorporated / /

Country

Netherlands / United States / /

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Facility

University of Manchester / Manchester University / Swinburne Institute of Technology / Explicit Token Store / Monash University / Massachusetts Institute of Technology / University of California / /

IndustryTerm

queue chips / programmable logic device / overflow chain / associative search / concurrent applications / bandwidth interprocessor networks / external queue chip / particular destination processor / format destination processor / streaming applications / speed interconnection network / compiler chain / technology mapper / interconnection network / density programmable logic devices / target device / communications overheads / image processing / image processing benchmark / computing / detection algorithm / performance using current hardware technologies / hardware technologies / /

Organization

Scientific and Industrial Research Organisation / MIT / Monash University Australia / University of California / Irvine / Matching Unit / Department of Electrical / Institute of Technology / University of Manchester / Manchester University / Pattern Analysis and Machine Intelligence / /

Person

A. Sloan / A. Young / G. Egan Figure / G. Egan An / Arvind / Gurd / G. K. Egan / M. Rawling / D. Abramson / Adam Sloan Greg Egan / /

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Position

producer / head / /

ProgrammingLanguage

Pascal / /

ProvinceOrState

New Jersey / California / Massachusetts / /

PublishedMedium

IEEE Transactions on Pattern Analysis and Machine Intelligence / /

Technology

adam / FPGA / RAM / Floating Point Unit / four processors / Token format destination processor / particular destination processor / image processing / external queue chip / destination processor / Pentium processor / FPGA technologies / hardware technologies / external queue chips / 4 Processors Interconnection Network Four Processor / however four processors / 256 processors / simulation / 4.3 Multi-processor / detection algorithm / least eight processors / /

URL

http /

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