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Electronic design automation / SystemVerilog / SystemC / E / Verilog / Statistical hypothesis testing / Bin / Test-driven development / Electronic engineering / Hardware description languages / Hardware verification languages
Date: 2013-06-06 20:23:27
Electronic design automation
SystemVerilog
SystemC
E
Verilog
Statistical hypothesis testing
Bin
Test-driven development
Electronic engineering
Hardware description languages
Hardware verification languages

CovVise: How We Stopped Throwing Away Interesting Coverage Data

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