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21	i AN EFFICIENT I/O AND CLOCK RECOVERY DESIGN FOR TERABIT INTEGRATED CIRCUITS A DISSERTATION Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Jitter Synchronization Bill Dally Electronic filter Thesis Integrated circuit Electronics Education Knowledge
22	Design Tradeoffs for Tiled CMP On-Chip Networks ∗ James Balfour , William J. Dally Computer Systems Laboratory Stanford University Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2006-09-12 12:06:57 Computer networking Network performance Throughput Network switch Routing Packet switching Channel Router Asynchronous Transfer Mode Computing Electronic engineering Network architecture
23	Scalable Opto-Electronic Network (SOENet) Amit K. Gupta, William J. Dally, Arjun Singh, and Brian Towles Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Electronics Switched fabric Fat tree InfiniBand Routing Topology Ethernet Clos network Node Network topology Computing Network architecture
24	Virtual- Channel Flow Controll William J. Dally Artificial Intelligence Laboratory and Laboratory for Computer Science Massachusetts Institute of Technology Cambridge, Massachusetts 02139 Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2008-04-03 14:20:06 Network performance OSI protocols Inter-process communication Traffic flow Throughput Network architecture Transmission Control Protocol Wormhole switching Packet switching Computing Computer networking Streaming
25	Route Packets, Not Wires: On-Chip Interconnection Networks William J. Dally and Brian Towles Computer Systems Laboratory Stanford University Stanford, CA 94305 {billd,btowles}@cva.stanford.edu Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Computer networking Computer memory Ethernet Network switch Content-addressable memory Cell Wormhole switching Network On Chip Computing Electronic engineering Electronics
26	Guaranteed Scheduling for Switches with Configuration Overhead Brian Towles and William J. Dally Abstract— In this paper we present three algorithms that provide performance guarantees for scheduling switches, such as Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Switches Analysis of algorithms Scheduling algorithms Computational complexity theory Scheduling Speedup Time complexity Graph coloring Crossbar switch Theoretical computer science Applied mathematics Mathematics
27	Globally Adaptive Load-Balanced Routing on Tori Arjun Singh, William J Dally, Brian Towles, and Amit K Gupta Computer Systems Laboratory, Stanford University arjuns, billd, agupta, btowles@cva.stanford.edu Abstract— Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Throughput Routing Parallel algorithm Non-blocking algorithm Concurrent computing Network performance Computing
28	GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks ∗ Arjun Singh , William J Dally , Amit K Gupta , Brian Towles Computer Systems Laboratory Stanford University {arjuns, billd, agupta, btowles}@cva.sta Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Throughput Routing Latency Shortest path problem Computing Theoretical computer science Network performance Mathematics
29	Adaptive Routing in High-Radix Clos Network John Kim, William J. Dally, Dennis Abts† † Stanford University Cray Inc. {jjk12, billd}@cva.stanford.edu Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2006-09-15 14:59:56 Network performance Internet Routing protocols Routing Throughput Latency Source routing Packet switching Forwarding plane Computer networking Computing Network architecture
30	A Delay Model for Router Micro-architectures Li-Shiuan Peh William J. Dally Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Network On Chip Routing Wormhole switching OSI protocols Throughput Router Network switch Forwarding plane Load-balanced switch Network architecture Computing Flow control

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