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Integrated circuits / Electronic design / Circuit extraction / Application-specific integrated circuit / Verilog / Adder / Datapath / Standard cell / Formal equivalence checking / Electronic engineering / Electronics / Electronic design automation


VIRAM-1 Vector Datapath University of California, Berkeley Joseph Gebis Description
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Document Date: 2000-01-20 23:40:07


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File Size: 279,12 KB

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Company

Hercules / /

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Facility

University of California / Vector Datapath University of California / /

IndustryTerm

built-in tool / online design / /

Organization

University of California / Berkeley / /

Person

Joseph Gebis / /

Position

graphics editor / Hercules Design Rules Check Cadence Schematic Editor / Tiler Cadence Graphics Editor / /

ProgrammingLanguage

Verilog / /

ProvinceOrState

California / /

Technology

logical unit / Simulation / Verilog / CAD / /

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