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Results: 440

#	Item
161	MEMORY AND CONTROL ORGANIZATIONS OF STREAM PROCESSORS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2009-11-09 11:38:32 Computer engineering GPGPU Stream processing Microprocessors Parallel computing Dynamic random-access memory Microarchitecture Central processing unit Computing Computer architecture Computer hardware
162	Route Packets, Not Wires: On-Chip Interconnection Networks William J. Dally and Brian Towles Computer Systems Laboratory Stanford University Stanford, CA 94305 {billd,btowles}@cva.stanford.edu Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Computer networking Computer memory Ethernet Network switch Content-addressable memory Cell Wormhole switching Network On Chip Computing Electronic engineering Electronics
163	Guaranteed Scheduling for Switches with Configuration Overhead Brian Towles and William J. Dally Abstract— In this paper we present three algorithms that provide performance guarantees for scheduling switches, such as Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Switches Analysis of algorithms Scheduling algorithms Computational complexity theory Scheduling Speedup Time complexity Graph coloring Crossbar switch Theoretical computer science Applied mathematics Mathematics
164	Globally Adaptive Load-Balanced Routing on Tori Arjun Singh, William J Dally, Brian Towles, and Amit K Gupta Computer Systems Laboratory, Stanford University arjuns, billd, agupta, btowles@cva.stanford.edu Abstract— Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Throughput Routing Parallel algorithm Non-blocking algorithm Concurrent computing Network performance Computing
165	LOAD-BALANCED ROUTING IN INTERCONNECTION NETWORKS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Management Routing Telecommunications engineering Throughput Computer network Load balancing Metrics Latency Scalability Network performance Computing Information technology management
166	775 IEEE TRANSACTIONS ON COMPUTERS, VOL. 39, NO. 6, JUNE 1990 Performance Analysis of k-ary n-cube Interconnection Networks Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2008-04-03 14:18:56 Information Low latency Electronic engineering Throughput Wormhole switching Channel Latency Routing Network topology Information theory Network performance Computing
167	1804 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002 A Low-Power Multiplying DLL for Low-Jitter Multigigahertz Clock Generation in Highly Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Oscillators Electronic design Radio electronics Digital electronics Electronic circuits Jitter Phase-locked loop Delay-locked loop Phase detector Electronic engineering Electronics Electromagnetism
168	GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks ∗ Arjun Singh , William J Dally , Amit K Gupta , Brian Towles Computer Systems Laboratory Stanford University {arjuns, billd, agupta, btowles}@cva.sta Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Throughput Routing Latency Shortest path problem Computing Theoretical computer science Network performance Mathematics
169	Adaptive Routing in High-Radix Clos Network John Kim, William J. Dally, Dennis Abts† † Stanford University Cray Inc. {jjk12, billd}@cva.stanford.edu Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2006-09-15 14:59:56 Network performance Internet Routing protocols Routing Throughput Latency Source routing Packet switching Forwarding plane Computer networking Computing Network architecture
170	A Delay Model for Router Micro-architectures Li-Shiuan Peh William J. Dally Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Network On Chip Routing Wormhole switching OSI protocols Throughput Router Network switch Forwarding plane Load-balanced switch Network architecture Computing Flow control

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