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CPU cache / Scratchpad memory / Direct memory access / Cache / AMD 10h / Memory hierarchy / Cell / Computer hardware / Computer memory / Computing


A run-time Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability George Nikiforos, George Kalokairinos, Vassilis Papaefstathiou, Stamatis Kavadias, Dionisis Pnevmatikatos and Manolis Katevenis
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Document Date: 2013-12-23 07:16:59

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City

Washington / DC / Palaiseau / Delft / /

Company

IBM / NI / Xilinx / /

Country

France / United States / Netherlands / /

/

Facility

Manolis Katevenis Institute of Computer Science / /

IndustryTerm

purpose systems / energy consumption / real-time applications / would-be single bank / runtime systems / stream processors / multicore computing systems / cache coherence protocol / user software demand / /

Organization

HiPEAC / European Commission / Manolis Katevenis Institute of Computer Science / IEEE Computer Society / /

Person

Stefan Steinke / Christos Sotiriou / Kenneth C. Yeager / Lee / Euriclis Kounalakis / Peter Marwedel / Peter Mattson / Georgi Gaydadjiev / John D. Owens / Michael Ligerakis / Dimitris Nikolopoulos / Spyros Lyberis / Xiaojun Yang / Dimitris Tsaliagos / Jung Ho Ahn / Brucek Khailany / Alex Ramirez / Scott Rixner / George Kalokairinos / /

Position

Cache Controller / simple round robin scheduler / DMA/Cache Controller / L2 cache controller / interface and cache controller / controller / arbiter / /

Product

Network Interface / MicroBlaze / /

ProgrammingLanguage

DC / /

Technology

FPGA / one processor / Programmable stream processors / two MicroBlaze processors / SRAM / cache coherence protocol / /

SocialTag