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Computer memory / Concurrency control / Microprocessors / Compiler construction / Memory barrier / Thread / Linearizability / Lock / Microarchitecture / Computing / Computer architecture / Computer hardware


A Tutorial Introduction to the ARM and POWER Relaxed Memory Models Luc Maranget INRIA Susmit Sarkar University of Cambridge
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Document Date: 2012-10-10 05:25:03

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File Size: 556,65 KB

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IBM / increment INC. / NVIDIA / /

Facility

POWER Relaxed Memory Models Luc Maranget INRIA Susmit Sarkar University of Cambridge October / Peter Sewell University of Cambridge Revision / /

IndustryTerm

web interface / ppcmem tool / to all processor / exploration tools / normal software development / software threads / individual processor / typical low-level concurrent algorithms / x86 processors / simpler hardware / on-line summary / litmus tool / nondeterministic systems / software development challenging / energy usage / /

Organization

Peter Sewell University of Cambridge Revision / POWER Relaxed Memory Models Luc Maranget INRIA Susmit Sarkar University of Cambridge / ARM / /

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Pseudocode Thread / Register Shadowing / Simple Message Passing / /

Position

Test MP / MP / correctly implemented scheduler / axiomatic model for POWER / programmer / /

ProgrammingLanguage

Java / R / C / C++ / /

Technology

Java / POWER processors / individual processor / example algorithm / typical low-level concurrent algorithms / Sequential Consistency / shared memory / x86 processors / /

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