Xilinx: Virtex-E 1.8V Field Programmable Gate Arrays

First Page		Document Content
Date: 2013-03-04 08:35:00 Reconfigurable computing Xilinx Integrated circuits Field-programmable gate array Embedded systems Delay-locked loop Joint Test Action Group Logic gate Low-voltage differential signaling Electronic engineering Electronics Digital electronics		Xilinx: Virtex-E 1.8V Field Programmable Gate Arrays Add to Reading List Source URL: www.xilinx.com Download Document from Source Website File Size: 1,44 MB Share Document on Facebook

	614 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 4, APRIL 2003 Jitter Transfer Characteristics of Delay-Locked Loops—Theories and Design Techniques DocID: 14toQ - View Document
	NETWORKS Principles of Robust Timing over the Internet The key to synchronizing clocks over networks is taming delay variability. Julien Ridoux and Darryl Veitch, University of Melbourne DocID: 14iRW - View Document
	1804 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002 A Low-Power Multiplying DLL for Low-Jitter Multigigahertz Clock Generation in Highly DocID: 13R5N - View Document
	[removed]On-Board Data Processing Part Time-Comparison-Equipment Processing Unit (TCE-PRO) KIUCHI Hitoshi, IMAE Michito, TAKAHASHI Yasuhiro, GOTOH Tadahiro, NAKAGAWA Fumimaru, FUJIEDA Miho, and HOSOKAWA Mizuhiko In satelli DocID: XWUa - View Document
	Systems Involving Group Delay DocID: 9ZjV - View Document