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#	Item
51	Instituto Politécnico Nacional Centro de Investigación en Computación Alligator OS: An embedded operating system T E S I S QUE PARA OBTERNER EL GRADO DE Add to Reading List Source URL: aalonso.files.wordpress.com Language: English - Date: 2011-11-08 00:11:22 Software System software Computer architecture Embedded Linux Build automation OpenEmbedded Xilinx Field-programmable gate array Wishbone Linux Udev
52	INSTITUTO POLITECNICO NACIONAL CENTRO DE INVESTIGACION EN COMPUTACION LABORATORIO DE MICROTECNOLOGIA Y SISTEMAS EMBEBIDOS Alligator_OS: An embedded OS Add to Reading List Source URL: aalonso.files.wordpress.com Language: English - Date: 2011-11-08 00:23:00 Computer architecture Computing Software Instruction set architectures Power Architecture Reconfigurable computing Xilinx Field-programmable gate array PowerPC Linux kernel Linux Embedded system
53	High Performance ECC over NIST Primes on Commercial FPGAs ECC 2008, Utrecht, September 22-24, 2008 Tim Güneysu Horst Görtz Institute for IT-Security Ruhr University of Bochum, Germany Add to Reading List Source URL: www.hyperelliptic.org Language: English - Date: 2008-10-27 20:01:32 Reconfigurable computing Electronic engineering Fabless semiconductor companies Electronics Computing Xilinx Field-programmable gate array Virtex Application-specific integrated circuit Logic block SciEngines GmbH
54	XPERTS CORNER Improving DDR SDRAM Efficiency with a Reordering Controller Virtex-6 memory controller achieves excellent sustained transfer rates for real-world workloads. Add to Reading List Source URL: www.xilinx.com Language: English - Date: 2011-02-15 17:23:45
55	www.rfel.com WHITEPAPER HALO™: A RECONFIGURABLE IMAGE ENHANCEMENT AND MULTI-SENSOR FUSION SYSTEM Add to Reading List Source URL: www.rfel.com Language: English - Date: 2015-07-29 06:53:37 Computer architecture Computing Computer engineering GPGPU Parallel computing Fabless semiconductor companies OpenCL compute devices Heterogeneous computing Field-programmable gate array Xilinx Graphics processing unit Digital signal processing
56	Master’s Thesis Balanced Routing of Dual-Rail Signals for DPA-Resistant Logic Styles in Xilinx FPGAs Vincent Immler Add to Reading List Source URL: www.emsec.rub.de Language: English - Date: 2014-11-21 04:42:23
57	X C E L L E N C E I N W I R E L E S S C O M M U N I C AT I O N S FPGAs Help Characterize Add to Reading List Source URL: www.xilinx.com Language: English - Date: 2015-05-29 22:25:18
58	CECS Seminar Series Presents Hardware Security in the Zynq All-Programmable Soc Dr. Steve Trimberger Xilinx Research Lab, San Jose, CA Add to Reading List Source URL: cecs.uci.edu Language: English - Date: 2015-09-30 19:48:13
59	Vivado Design Suite User Guide Implementation UG904 (v2014.4) November 19, 2014 Add to Reading List Source URL: www.xilinx.com Language: English - Date: 2015-05-30 02:35:01
60	Domain-Specific Programming of Very High Speed Packet Processing Gordon Brebner Xilinx Labs San José, USA Add to Reading List Source URL: www.xilinx.com Language: English - Date: 2012-07-25 16:19:31