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A Low-Complexity Dynamic Translator for x86
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Document Date: 2007-09-20 09:41:43

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File Size: 149,22 KB

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City

Baltimore / /

Company

IDT / Systems Research Laboratory / PDBR Hardware / VDebug Hardware / VMware / Intel / /

Country

United States / /

Currency

USD / /

Facility

Systems Research Laboratory The Johns Hopkins University / /

IndustryTerm

minimal hardware / device hardware / guest operating systems / guest with direct access to hardware / management protocol / machine-specific hardware / kernel debugging tool / hardware device / Static binary rewriting tools / /

Organization

The Johns Hopkins University / /

Person

Jonathan S. Shapiro / Swaroop Sridhar / /

Position

supervisor / instruction translator / user/supervisor / equal parts binary translator / low-complexity dynamic translator / code translator / /

ProvinceOrState

Maryland / /

Technology

virtual machine / conventional Pentium-family processors / Paging / caching / simulation / virtual memory / operating system / operating systems / management protocol / /

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