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Instruction set architectures / Computer memory / X86 architecture / X86-64 / Java memory model / X86 / Memory barrier / Spinlock / Memory ordering / Low-level programming language / Itanium / ARM architecture


Relaxed memory models must be rigorous ˇ c´ık3 Susmit Sarkar2 Francesco Zappa Nardelli1 Peter Sewell2 Jaroslav Sevˇ Luc Maranget1 Mark Batty2 Jade Alglave1 1
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Document Date: 2012-09-10 07:41:00

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