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ABSTRACT Title of dissertation: MODERN DRAM MEMORY SYSTEMS: PERFORMANCE ANALYSIS AND A HIGH PERFORMANCE, POWER-CONSTRAINED
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Document Date: 2006-04-10 12:09:53


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File Size: 3,51 MB

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Company

Logic Optimized Process Technologies / MODERN DRAM MEMORY SYSTEMS / Device Configuration Trade / Bank Activation Window Limited / /

Currency

AMD / /

Event

FDA Phase / /

Facility

College Park / University of Maryland / /

IndustryTerm

proposed rank hopping scheduling algorithm / computer systems / close-page systems / memory systems / open-page systems / /

Organization

DRAM-Bank-Centric Request Queuing Organization / Graduate School / Row Access Command / Memory System Organization / Precharge Command / Organization of Dissertation / Memory Module Organization / Bus Interface Unit / University of Maryland / College Park / Contents CHAPTER / Associate Professor Bruce L. Jacob Department of Electrical and Computer Engineering / DRAM Device Organization / Advisory Committee / DRAM System Organization / System Organization / /

Person

Bruce L. Jacob / Shuvra S. Bhattacharyya Associate Professor Tsung / Donald Yeung Associate Professor Charles / Charles B. Silio Jr. / Tsung Chin Associate Professor Donald Yeung / David Tawei Wang / /

Position

DRAM Memory Controller / Chair / Associate Professor / /

Product

DDR2 / /

ProgrammingLanguage

FP / Fortran 77 / Fortran 90 / /

ProvinceOrState

Maryland / /

Technology

proposed rank hopping scheduling algorithm / cache-limited processors / 182 Power-Constrained DDRx Scheduling Algorithm / 35 2.11 Process Technology / Computing DRAM Protocol / 105 DDR2 SDRAM Protocol / 62 DRAM Memory Access Protocol / Computational Chemistry / Rank Hopping Scheduling Algorithm / Caching / SDRAM / PERFORMANCE ANALYSIS AND SCHEDULING ALGORITHM / Simulation / /

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