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Signoff / Synopsys / Static timing analysis / Signal integrity / Electronic circuit simulation / Delay calculation / Logic simulation / Parasitic extraction / SPICE / Electronic engineering / Electronic design automation / Digital electronics


Datasheet NanoTime Transistor-level Static Timing Analysis Solution for Custom Designs Overview
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Document Date: 2015-02-27 00:06:11

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File Size: 244,66 KB

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