Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access ∗ Niladrish Chatterjee‡ ‡ University Manjunath Shevgoor‡ Rajeev Balasubramonian‡ - Synchronous dynamic random-access memory - Document - PDFSEARCH.IO - Document Search Engine

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	Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access ∗ Niladrish Chatterjee‡ ‡ University Manjunath Shevgoor‡ Rajeev Balasubramonian‡ Add to Reading List Document Date: 2012-11-05 13:54:51 Open Document File Size: 2,15 MB Share Result on Facebook Company CWF / Nvidia Corporation / Intel Labs / RLDRAM / / Currency AMD / / / Event FDA Phase / / Facility The RL AD bar / University of Utah / University Manjunath Shevgoor‡ Rajeev Balasubramonian‡ Zhen Fang§† Ramesh Illikkal∞ Ravi Iyer∞ / bar RL OR / / IndustryTerm energy gap / memory system energy / higher bank count / higher bank-turnaround time / energy advantages / memory energy / overall system energy / lower energy / memory systems / low bank-turnaround time / bank count / bank-turnaround / system energy / greater energy savings / energy savings / energy / fault tolerance solutions / overall system energy consumption drops / x9 chip / energy consumption / energy consumption increases / bank / energy efficiency / computing / bank activations / low-energy / system energy savings / network processing / activation energy / low-energy region / parity solution / power-sensitive systems / energy characteristics / bank-turnaround time / energy bottleneck / performance routers / bank level parallelism / higher bank counts / homogeneous memory systems / bandwidth applications / memory energy reduction / system energy consumption / low-energy portions / energy cost / out-of-order processor / bank counts / maximum energy savings / / MarketIndex OpenMP NAS Parallel / / NaturalFeature DRAM channel / RLDRAM channel / / Organization LPDRAM DIMMs / University of Utah / US Federal Reserve / National Science Foundation / DDR3 DIMMs / RLDRAM Reduced Latency DRAM / LPDRAM Low Power DRAM / / Person Ramesh Illikkal∞ Ravi Iyer / Al Davis / Rajeev Balasubramonian‡ Zhen Fang / / Position head / channel and memory controller / single memory controller / bus and memory controller / independent controller / representative / forward / memory controller / programmer / driver / ory controller / candidate for power optimizations / additional memory controller / power model for LPDDR2 / LPDRAM memory controller / controller / / Product STREAM / RL / L2 / / ProvinceOrState Utah / / Technology RLDRAM3 chip / performance routers / regular DDR chips / 9 chips / SRAM / low-power DRAM chips / LPDRAM processor / 8 LPDDR2 chips / mobile devices / CMP / cycle Cache Hierarchy L1 I-cache L1 D-cache L2 Cache Coherence Protocol / simulated processor / out-of-order processor / LPDDR2 chips / LPDRAM chip / low-energy DRAM chips / LPDRAM chips / DDR chip / DRAM chip / LPDDR3 chips / Methodology Processor / DDR3 chip / 16 RLDRAM3 chips / DDR3 chips / individual DDR chips / mobile DRAM chips / one x9 chip / 32 LPDDR2 chips / 1 RLDRAM3 chip / DDR3 DRAM chips / 8 low-power LPDDR chips / 9 DDR3 chips / 16 chips / 4 chips / SDRAM / simulation / 9 DDR chips / DRAM chips / LPDDR2 chip / / SocialTag Digital media DDR3 SDRAM DIMM Synchronous dynamic random-access memory Dynamic random-access memory DDR SDRAM CAS latency DDR2 SDRAM Prefetch buffer Computer memory