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Telecommunications engineering / POWER4 / Jitter / Phase-locked loop / Clock signal / Synchronous dynamic random-access memory / Electronic engineering / Electronics / Computer buses


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Document Date: 2013-07-27 22:49:06

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File Size: 121,60 KB

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IBM / Bandwidth & Cycle Limited / /

IndustryTerm

costly manufacturing / particular chip / /

Person

Edgar Cordero Daniel Dreps Michael / Frank Ferraiolo Edgar Cordero Daniel / Bradley McCredie Worse Case Timing / Daniel Dreps Michael Floyd Kevin / /

Technology

particular chip / CYCLE BUS BUS LOGIC LOGIC PLL CHIP / 1999 System Configuration CHIP / PowerPC processor / SRAM / /

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