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Central processing unit / Instruction set / Microarchitecture / Instruction cycle / Addressing mode / Parallel computing / Superscalar / Transport triggered architecture / Computer architecture / Computer engineering / Computer hardware


A PROCESSOR ARCHITECTURE Mark R. Thistle Institute for DefenseAnalyses SupercomputingResearchCenter Lanham,Maryland 20706
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Document Date: 2003-06-11 14:31:52

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File Size: 947,70 KB

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Company

Control Data / Tera Computer Company / Texas Instruments / /

Currency

USD / /

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Facility

Thistle Institute / Supercomputing Research Center / /

IndustryTerm

bank-freebits / individual processors / appropriate register bank / register memory bank / bank issue cycles / bank copiesin / shared memory systems / i-streamsper processor / memory bank conflicts / software approach / register banking scheme / horizontal processors / Technology considerationsprevent / describesthe interconnection network / bank schedules / free bank cycles / Bank readinessis / instruction execution register banking / nearestneighbor network / Bank registerwrite / bank conflicts / register bank cycles / register banking constraints / consecutive bank cycles / Bank selection / possible banks / register banking idea / register bank schedule / selection algorithm / interconnection network / sameregister bank / chosen bank / bank / free banks / free register bank cycle / round-robin algorithm / Memory referencesmust traversethe interconnection network / interconncction network / identical scalar processors / consecutive bank access cycles / register bank / memory banks / /

NaturalFeature

Multiple Data stream / Multiple Instruction stream / Data stream / Single Instruction stream / /

Organization

Supcrcomputing Research Center / PROCESSOR ARCHITECTURE Mark R. Thistle Institute for DefenseAnalyses SupercomputingResearchCenter Lanham / United Nations / Supercomputing Research Center / /

Person

Burton J. Smith / William E. Holmes / David L. Smitley / Steven Melvin / James T. Kuehn / Fred A. More / Daniel J. Kopetzky / Tera ComputerCompany / /

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Position

Chief Architect / programmer / /

ProgrammingLanguage

FORTRAN / /

ProvinceOrState

Maryland / /

Technology

selection algorithm / Horizon processor / 3-D / 3.2 Functional Unit Model Each processor / identical scalar processors / individual processors / round-robin algorithm / operating system / shared memory / i-streamsper processor / Flow control / source processor / Simulation / virtual memory / 2.2 ProcessorModel The Horizon processor / Parallel Processing / /

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