View Document Preview and Link Document Date: 2011-05-02 09:20:13 Open Document File Size: 43,03 KB Share Result on Facebook
City Mannheim / / Company System Area Networks / Hewlett-Packard / / Facility O bridge / / IndustryTerm large systems / distributed directory-based cache coherence protocol / channel protocols / interconnection network / interconnect technologies / interface hardware / distributed processing / multistage switching networks / software protocol-paradigm translation / phase transaction protocol / cache coherence protocol / / Organization National Supercomputer Centre / Universität Mannheim WS03 / / Person Selected Write / Processor A Processor / Selected Locks / Block Write / Selected Read / / Position cache controller / bytes Head / MANAGER request response response Input Queues Output Queues In Fifo Data In request Stripper Out Fifo Bypass Fifo Out Mux Data Out 16bits / CPU/Cache SCI-Registers Rety Screen PACKET MANAGER / bytes Head Head / Head / / ProgrammingLanguage C / / Technology Cut-through routing Processor / Packet switching / four phase transaction protocol / flow control / ATM / Gigabit / shared memory / cache coherence protocol / distributed directory-based cache coherence protocol / I/O channel protocols / / URL www.dolphinics.com / http / SocialTag 
Vorlesung Rechnerarchitektur 2 Seite 178