Retiming

#	Item
31	Exploration of RaPiD-style Pipelined FPGA Interconnects Akshay Sharma1, Katherine Compton2, Carl Ebeling3, Scott Hauck1 Add to Reading List Source URL: www.ee.washington.edu Language: English - Date: 2005-07-19 18:43:06 Computer hardware C-slowing Field-programmable gate array Parallel computing Retiming Processor register Cell Classes of computers Electronic engineering Computer architecture Central processing unit
32	PDF Document Add to Reading List Source URL: sites.google.com Language: English Electronics Clock signal Field-programmable gate array Clock skew Algorithm Electronic design automation Electronic engineering Formal methods Retiming