<--- Back to Details
First PageDocument Content
Minicomputers / Instruction set architectures / Central processing unit / PDP-11 / Computer memory / PDP-10 / PDP-8 / Unibus / Programmed Data Processor / Computing / Computer hardware / Classes of computers
Minicomputers
Instruction set architectures
Central processing unit
PDP-11
Computer memory
PDP-10
PDP-8
Unibus
Programmed Data Processor
Computing
Computer hardware
Classes of computers

Add to Reading List

Source URL: research.microsoft.com

Download Document from Source Website

Share Document on Facebook

Similar Documents

Concurrency control / Transaction processing / Computing / Data management / System software / Transactional memory / Benchmark / Lock / Parallel computing / Linearizability / Consistency model

ARCHITECTURES FOR TRANSACTIONAL MEMORY A DISSERTATION SUBMITTED TO THE DEPARTMENT OF COMPUTER SCIENCE AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY

DocID: 1xUpu - View Document

Mathematics / Formal languages / Temporal logic / Syntax / Metalogic / Logic / Metaphilosophy / Model theory / Linear temporal logic / Interpretation / Computation tree logic / Variable

Towards Algorithmic Synthesis of Synchronization for Shared-Memory Concurrent Programs Roopsha Samanta Computer Engineering Research Centre, The University of Texas at Austin.

DocID: 1xTqp - View Document

Improved Semantic Representations From Tree-Structured Long Short-Term Memory Networks Kai Sheng Tai, Richard Socher*, Christopher D. Manning Computer Science Department, Stanford University, *MetaMind Inc. fo

DocID: 1xTeG - View Document

Machine Quilters Exposition Photo Memory Stick MQX Quilt Festival-Midwest 2016 ™ Instructions for Viewing High Resolution Images on your Computer

DocID: 1vht1 - View Document

A Memory Coherence Technique for Online Transient Error Recovery of FPGA Configurations Wei-Je Huang and Edward J. McCluskey CENTER FOR RELIABLE COMPUTING Computer Systems Laboratory, Department of Electrical Engineering

DocID: 1vgLJ - View Document