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Datasheet Proteus Full-Chip Mask Synthesis Overview
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Document Date: 2014-11-07 14:34:24


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File Size: 2,15 MB

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Company

ProGen / Next-Generation Verification Proteus MLO Highly-Scalable Manufacturing / Proteus Pipeline Technology / Synopsys Inc. / Highly Utilize Expensive Hardware Resources / Intel / /

Country

United States / /

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Facility

Proteus Pipeline / /

IndustryTerm

x86 hardware / technology nodes / lithographic process solutions / concurrent processing / simulation algorithms / technology needs / synchronal processing / simulation algorithm / distributed processing / hierarchical processing / multiCPU parallel processing / manufacturing environment / hierarchy processing / concurrent tapeout flow / manufacturing link / mask synthesis products / parallel processing / serial manufacturing flows / manufacturing / expensive hardware / manufacturing tools / concurrent data-processing mode / hierarchical management / latter applications / x86 architecture processors / inverse-mask technology / manufacturing information / optimized general purpose hardware / /

Person

Layout Viewer / /

Position

Editor / Model Calibrator / Optimized General / local sales representative / CoO / /

Technology

x86 architecture processors / simulation algorithm / Default algorithms / inverse-mask technology / simulation algorithms / lithography / simulation / flash / parallel processing / specific technology / GUI / /

URL

www.synopsys.com / http /

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