Introducing 28-nm Stratix V FPGAs: Built for Bandwidth Dan Mansur Sergey Shumarayev August 2010 - Nios embedded processor - Document - PDFSEARCH.IO

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	Introducing 28-nm Stratix V FPGAs: Built for Bandwidth Dan Mansur Sergey Shumarayev August 2010 Add to Reading List Document Date: 2013-07-28 00:16:39 Open Document File Size: 1,63 MB Share Result on Facebook Company PCS 28G LC / Hard PCS Transceiver PMA 12G LC / Altera Corporation / TSMC / High-End Systems / PCS Hard PCS Transmit Clock Source Clock Networks / enabling up to 44 independent data rates Hard PCS Hard PCS Hard PCS Transmit Clock Source Clock Networks / / Country United States / / Event Natural Disaster / / IndustryTerm bandwidth systems / on largest device / continuous bank / extra-low leakage devices / / Person Dan Mansur Sergey Shumarayev August / / Product CYCLONE / / Technology Ethernet / FPGA / RAM / DSP / / SocialTag Integrated circuits Field-programmable gate array Nios embedded processor TSMC MOS Technology SID Cyclone Electronic engineering Electronics Altera

Introducing 28-nm Stratix V FPGAs: Built for Bandwidth Dan Mansur Sergey Shumarayev August 2010Add to Reading List