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OpenCL / Field-programmable gate array / Block cipher modes of operation / Parallel computing / Cryptography / GPGPU / Advanced Encryption Standard


White Paper 40Gbit AES Encryption Using OpenCL and FPGAs Introduction
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Document Date: 2012-11-08 15:49:46

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File Size: 415,76 KB

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Company

FPGAs White Paper / Altera / GPU / Mix Columns / Intel / The AES / Amdahl / Accelerator 3 40Gbit AES Encryption Using OpenCL / /

Country

United States / /

Event

Product Release / /

IndustryTerm

high speed host communications / host processor / distinct processing stages / kernel processing time / work / accelerator technology / parallel processing / hybrid computing model / computing / stream processors / encryption algorithm / /

NaturalFeature

FPGA AES streams / /

Organization

U.S. government / European Central Bank / U.S. Securities and Exchange Commission / /

Position

designer / programmer / /

Product

OpenCL / OpenCL The / PCIe-385N accelerator card / PCIe-385N / /

ProgrammingLanguage

C / /

Technology

Encryption / mode decryption CTR encryption / Ethernet / FPGA / host processor / mode encryption / encryption algorithm / API / Technology E5503 Xeon Processor / 2048 stream processors / Xeon E5503 processor / SRAM / FPGA accelerator technology / parallel processing / FPGA technologies / /

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