Multicore

Results: 503



#Item
61

Servet: A Benchmark Suite for Autotuning on Multicore Clusters Jorge Gonz´alez-Dom´ınguez, Guillermo L. Taboada, Basilio B. Fraguela, Mar´ıa J. Mart´ın, Juan Touri˜no Computer Architecture Group Department of Ele

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Source URL: www.des.udc.es

- Date: 2010-05-03 09:39:58
    62

    Transactional IPC in L4/Fiasco.OC Can we get the multicore case verified for free? Till Smejkal, Adam Lackorzynski, Benjamin Engel and Marcus Völp Operating Systems Group Technische Universität Dresden

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    Source URL: www.mpi-sws.org

    - Date: 2016-07-14 16:23:27
      63

      Multicore Application Debugging Multicore Debugging Challenges for the Automotive Domain 1. International Workshop on Multicore Application Debugging (MAD 2013)

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      Source URL: www.mad-workshop.de

      - Date: 2016-03-22 12:43:37
        64

        Optimizing MPI Communication within large Multicore nodes with Kernel assistance St´ephanie Moreaud, Brice Goglin, David Goodell, Raymond Namyst To cite this version: St´ephanie Moreaud, Brice Goglin, David Goodell, Ra

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        Source URL: hal.inria.fr

        - Date: 2016-06-15 13:51:13
          65

          Programmazione di Sistemi Multicore A.AProf. Irene Finocchi

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          Source URL: twiki.di.uniroma1.it

          - Date: 2015-12-28 11:42:29
            66

            Programmazione di Sistemi Multicore A.AProf. Irene Finocchi

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            Source URL: twiki.di.uniroma1.it

            - Date: 2015-11-18 07:12:19
              67

              Hybrid PGAS Runtime Support for Multicore Nodes Filip Blagojevi´c, Paul Hargrove, Costin Iancu, Katherine Yelick Lawrence Berkeley National Laboratory {fblagojevic, phhargrove, cciancu, kayelick}@lbl.gov Abstract

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              Source URL: crd.lbl.gov

              - Date: 2012-10-24 14:13:45
                68

                Programmazione di Sistemi Multicore A.AProf. Irene Finocchi

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                Source URL: twiki.di.uniroma1.it

                - Date: 2015-11-01 03:58:37
                  69

                  Good Programming in Transactional Memory Game Theory Meets Multicore Architecture Raphael Eidenbenz and Roger Wattenhofer Computer Engineering and Networks Laboratory (TIK), ETH Zurich, Switzerland {eidenbenz,wattenhofer

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                  Source URL: www.tik.ee.ethz.ch

                  - Date: 2015-05-18 12:16:06
                    70

                    Hierarchically Tiled Arrays Vs. Intel Threading Building Blocks for Programming Multicore Systems ? Diego Andrade1 , James Brodman2 , Basilio B. Fraguela1 , and David Padua2 1

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                    Source URL: www.des.udc.es

                    - Date: 2007-12-18 11:10:37
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